Differential clock distribution has long played a critical role in, e.g., INTEL's IA32 and Itanium systems based on the parallel front side bus (FSB) and more recently in high-speed differential (HSD) serial links, such as common system interface (CSI), fully buffered dual in-line memory module (FBD), and PCI-Express. As a hybrid of common-clock and source-synchronous signaling, the FSB has always depended on tightly controlled clock skew characteristics for discrete clock components. Clock skew refers to a propagation delay difference between receipts of clock transitions at different locations within a system. Clock skew forces the design of faster and more complex components downstream to compensate for the propagation delay.
With FSB speeds increasing towards, e.g., 1600 million transfers per second (MT/s) for the next generation of digital enterprise systems, clock skew is a more significant portion of the total cycle time. Thus, the static clock skew should be minimized. Static clock skew is the sum of the pin-to-pin output skew, interconnect skew, and input capacitance delta induced skew.
One of the key specifications for FSB differential clocking is pin-to-pin output skew, which is controlled for as many as five agents in a multiprocessor design. Current solutions can do very little to improve the static clock skew performance of discrete clock drivers, the best of which now guarantee about plus or minus 50 picoseconds (ps) for pin-to-pin output skew. For example, current solutions involve selecting lengths for the metal lines between the clock driver outputs and the differential clock loads to minimize clock skew via propagation delay times.